The present invention relates to clamping circuits for clamping input signals in the process of analog-to-digital conversion (A/D conversion), and more particularly relates to a clamping circuit and digital camera system mounting the clamping circuit where imaging signals in a video equipment such as digital camera using a solid-state imaging device such as CCD (Charge Coupled Device) are processed so that the signals become clamped to a digitally set value after A/D conversion.
Being developed in recent years among video equipment using an imaging device such as solid-state imaging device are digital cameras, etc., where analog image signals are converted into digital image signals so as to be stored for example to a memory. Of the image signals treated in such a video equipment, DC component is sometimes lost or DC component itself may fluctuate in the process up to their inputting into a digital signal processing circuit for example when a capacitance coupling amplifier is used to amplify image signals. In such a case, signals are different in pedestal level (blanking level: reference potential) between dark frame (black level) and bright frame, resulting in such disadvantages as that a portion to be displayed theoretically as white in a frame becomes gray or that change in contrast occurs in a frame. For this reason, the image signals as they are cannot be subjected to various correction or be accurately treated in a digital signal processing.
In video equipment, therefore, black level, i.e., pedestal level must be fixed before the digital signal processing. In digital cameras using a solid-state imaging device such as CCD, a portion of an invalid imaging area 102 occurring on the periphery of an effective imaging area 103 of a solid-state imaging device 101 as shown in FIG. 1 is totally concealed from light as portion for such a black level. An accurate DC component with a smaller error is regenerated from image signals with using the concealed-from-light optical black (OB) portion 104. The regenerated DC component is then superimposed on image signals to forcibly fix a reference black level, i.e., pedestal level.
A prior-art feedback clamping circuit for effecting regeneration process of such a DC component is disclosed for example in Japanese Patent Application Laid-Open Publication Hei-6-46287.
FIG. 2 is a block diagram showing an example of the prior-art feedback clamping circuit disclosed in the above publication. The feedback clamping-circuit includes: a differential amplifier 201; A/D converter 202; a first register 203; a subtracter 204; an adder 205; a second register 206; D/A converter 207; and a timing generator 208.
The differential amplifier 201 clamps analog image signals inputted into the differential amplifier by inputting a correction potential to an inversion input section of the differential amplifier 201. The A/D converter 202 converts the analog image signals clamped at the differential amplifier 201 into digital signals. The first register 203 retains black level (pedestal level) for the clamped digital image signals at timings given from the timing generator 208.
The subtracter 204 detects an error between the pedestal level retained at the first register 203 and a previously set normal pedestal level. The adder 205 adds together the error in potential that is detected at the subtracter 204 and a correction potential computed at the processing at the last time to update correction potential. The second register 206 retains the updated correction potential at timing from the timing generator 208. The D/A converter 207 converts the updated new correction potential into an analog signal and feeds it back to the inversion input section of the differential amplifier 201 as a clamping potential for input analog image signal.
The operation of the above described prior-art feedback clamping circuit will now be described with reference to FIGS. 2 and 3A to 3C. FIGS. 3A to 3C are timing charts showing signal waveforms for explaining operation of the prior-art feedback clamping circuit. The horizontal direction in FIGS. 3A to 3C represents timing axis and the vertical direction represents signal axis. FIG. 3A indicates an image signal (signal A) at the pedestal level of which DC component has been lost; FIG. 3B indicates a clamping timing signal (signal B); and FIG. 3C indicates a set signal (signal C).
First, when an analog image signal (signal A of FIG. 3A) without having DC component is inputted to the differential amplifier 201, the input analog image signal is clamped at the differential amplifier 201 by means of a level correction potential transmitted from D/A converter 207 and is provided as output. The clamped analog image signal is converted into a digital signal at A/D converter 202 and is outputted to an outputting section, usually a digital signal processing section (not shown) and to the first register 203.
When the clamped digital image signal is inputted to the first register 203, a pedestal level of the input digital image signal is extracted/retained by means of a clamp timing signal corresponding to the timing of pedestal (blanking) of the digital image signal and is provided as output. The clamp timing signal is the signal (signal B of FIG. 3B) which is generated at the timing generator 208 and is transmitted respectively to the first register 203 and to the second register 206.
Next, when the pedestal level outputted from the first register 203 is inputted to the subtracter 204; a previously set normal pedestal level is subtracted from such pedestal level at the subtracter 204. The result of subtraction at the subtracter 104 is a data indicating an error between the pedestal level of the input digital image signal and the previously set normal pedestal level (set value shown in FIG. 2).
Further, when the above error data is inputted to the adder 205, the adder 205 adds together the error data and a correction potential from the second register 206 that has been given to the differential amplifier 201 through D/A converter in the processing of last time, and outputs the result as a new correction potential. At this time, if an overflow occurs of the correction potential output value from the adder 205, a maximum value thereof is outputted, while a value of zero is outputted if it is a minus.
The new correction potential outputted from the adder 205 is inputted to the second register 206, and it is updated and retained for one horizontal period by a set signal (signal C of FIG. 3C) that is delayed from the clamp timing signal (signal B of FIG. 3B) and is generated at one timing during a horizontal blanking interval. The set signal is inputted to the second register 206 from the timing generator 208 so that the correction potential outputted from the second register 206 is updated every time when the above described clamp timing signal is generated. The new correction potential outputted from the second register 206 is converted into an analog signal by D/A converter 207 and is inputted to the differential amplifier 201. The input analog image signal without having DC component is thereby clamped to a new correction potential, i.e., receives a DC component.